The present invention relates to a method of fabricating a semiconductor device, and particularly to a mask pattern aligning technique for aligning a mask pattern using an alignment mark of a thin semiconductor layer as a reference point.
Recently semiconductor devices have become increasingly more integrated and microminiaturized, and mask pattern alignment has required highly developed techniques.
In the mask pattern aligning technique for a semiconductor device having a MOSFET, the mask pattern alignment for forming the gate electrode of the MOSFET in its device area is very critical. This point will be explained with reference to FIGS. 1A and 1B.
A device area on a semiconductor substrate is isolated by a thick field oxide, and a polysilicon layer is formed on the entire surface of the substrate and patterned with a mask pattern aligned with the device area to form the gate electrode. In forming a MOSFET based on 0.5 .mu.m design rules, the width of the gate electrode is designed to be 0.5 .mu.m, and an overlap of the gate electrode from the device area is designed to be 0.5 .mu.m as shown in FIG. 1A. If the misalignment between the device area and the gate electrode is more than 0.5 .mu.m, the source region and the drain region in the device area short each other out.
Accordingly the precision of the mask pattern alignment for forming the device area and the gate electrode requires an alignment precision of 0.5 .mu.m.
In the meantime, to suppress degradation of the characteristics of a CMOSFET due to the inter-device interference caused by latchup, an SOI (Silicon On Insulator) technique for fabricating devices in small islands of silicon on an insulating substrate is noted. Even in forming the CMOSFETs on the SOI substrate, a high alignment precision as described above for aligning the mask pattern for forming the gate electrode with the device electrode is required.
With reference to FIGS. 2A to 2H, the conventional mask pattern alignment will be explained by means of the case that a MOSFET is formed on an SOI substrate prepared by the so-called bonding technique.
FIGS. 2A to 2H show sectional views at the respective steps of the conventional method of fabricating a semiconductor device. Each drawing depicts, on the left side, a device area 6 where a device is to be formed, and on the right side, an alignment mark area 7 where an alignment mark is to be formed. In each drawing, for illustrative purposes, the device area 6 is enlarged widthwise on a larger scale than the alignment mark area 7.
As shown in FIG. 2A, a first semiconductor substrate 9 is selectively etched in the device area 6 and in the alignment mark area 7 so as to form a convex portion 9a in the device area layer and a convex portion 9b in the alignment mark area.
Then, as shown in FIG. 2B, an insulating layer 11 is formed over the entire surface of the semiconductor substrate 9 including the convex portions 9a and 9b.
Next, as shown in FIG. 2C, the surface of the insulating layer 11 is polished so as to present an isolation insulating layer 11a having a flat upper surface, which is left on top of the convex portions 9a and 9b.
Then, as shown in FIG. 2D, the first semiconductor substrate 9 is turned over and is laid on a second semiconductor substrate 12 for support purposes through the isolation insulating layer 11a which is bonded to substrate 12 by applying voltage and heat.
Subsequently, as shown in FIG. 2E, the backside of the first semiconductor substrate 9 is etched or polished until the isolation semiconducting layer 11a is exposed with the originally convex portion 9a of the device area and the originally convex portion 9b of the alignment mark area embedded as islands in the isolation semiconducting layer 11a. The originally convex portions 9a and 9b are thus isolated from each other by the isolation insulating layer 11a. Thus, an SOI substrate 8 is completed.
Then, as shown in FIG. 2F, insulating layers 13a and 13b are formed respectively on the surfaces of the device area portion 9a and of the alignment mark portion 9b. The insulating layer 13a is to be the gate insulating layer for the device area 6.
Subsequently, as also shown in FIG. 2F, a polysilicon layer 14 is formed on the entire surface of the SOI substrate 8 so as to cover the insulating layers 13a and 13b. The polysilicon layer 14 is to be the gate electrode for the device area 6.
Then, as also shown in FIG. 2F, a resist layer 15 is formed on the polysilicon layer 14. A mask 16 is then aligned with the alignment mark 9b as the reference point. A mask pattern 16a on the aligned mask 16 is transferred to the resist layer 15 by photolithography. Then the resist layer 15 is developed, and resist patterns 15a and 15b are formed.
Subsequently, as shown in FIG. 2G, the polysilicon layer 14 is selectively etched using the resist patterns 15a and 15b as the masks. Thus, a gate electrode 14a is formed in the device area 6 and a polysilicon layer 14b is formed in the alignment mark area.
Then, as shown in FIG. 2H, dopant ions are implanted into the device area layer 9a using the gate electrode 14a as the mask so as to form a source region 17a and a drain region 17b. Next, an insulating layer 19 is formed in the device area so as to cover the gate electrode 14a. Then a source electrode 18a connected to the source region 17a, and a drain electrode 18b connected to the drain region 17b are formed, and a MOSFET is thus completed.
As described above, in the conventional method of fabricating the semiconductor device, when the polysilicon layer 14 is patterned to form the gate electrode 14a, following the fabrication of the SOI substrate 8, as shown in FIG. 2F, the alignment mark 9b, which has been formed at the time of the formation of the device area layer 9a, is buried in the isolation insulating layer 11a. According, the alignment mark 9b, which has no step contour and is buried under the polysilicon layer 14, cannot be detected using a conventional pattern detection method which depends on step contours.
In addition to the bonding technique, SOI substrates can be fabricated using a SIMOX (Separation by Implanted Oxygen) technique, a laser recrystallization technique for recrystallizing a polysilicon layer by a laser beam, and other techniques. When a semiconductor device is fabricated on an SOI substrate fabricated by a technique other than a bonding technique, it is also a problem that the contrast due to a reflectance difference cannot be easily directed when both the semiconductor layer on the isolation insulating layer and the alignment mark are very thin in accordance with the recent higher integration and microminiaturization of semiconductor devices.